![]() V OUT = V CC - V BE4 - V D1 V OUT = 5 - 0.6 - 0.6 = 3.8V Point P1: V IN = 0.5, V OUT = 3.8VĪs the input voltage is slightly increased, the above state continues until, with Q 1 on and in saturation, the voltage at the base of Q 2 rises to the point of conduction. While there is no load present, there are leakage currents flowing in the output stage which allow the transistor Q 4 and the diode D 1 to be barely conducting in the ON state. This ensures that Q 2 is off which, in turn, means that Q 3 is off. Since the only source of collector current is the leakage of Q 2, Q 1 will be driven into saturation. With the input near 0 volts and the base current supplied to Q 1, this transistor can conduct in the forward mode. Figure 6 TTL inverter input vs output transfer curve ![]()
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